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cat93c76 (rev. a) ? 2008 scillc. all rights reserved 1 doc. no. md-1090 rev. d characteristics subject to change without notice 8k-bit microwire serial eeprom features ? high speed operation: 3mhz @ v cc 2.5v ? low power cmos technology ? 1.8 to 5.5 volt operation ? selectable x8 or x16 memory organization ? self-timed write cycle with auto-clear ? software write protection ? power-up inadvertant write protection ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature ranges ? sequential read ? ?green? package option available pin configuration pdip (l), soic (v) tssop (y), tdfn (zd4) cs 1 8 v cc sk 2 7 nc di 3 6 org do 4 5 gnd pin function pin name function cs chip select sk serial clock input di serial data input do serial data output v cc power supply gnd ground org memory organization nc no connection note: when the org pin is connected to v cc , x16 organization is selected. when it is connected to ground, x8 organization is selected. if the org pin is left unconnected, then an internal pull-up device will select x16 organization. description the cat93c76 is an 8k-bit serial eeprom memory device which is configured as either registers of 16 bits (org pin at v cc or not connected) or 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c76 is manufactured using catalyst?s advanced cmos eeprom floating gate technology. the device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. the device is available in 8-pin pdip, soic, tssop and 8-pad tdfn packages. functional symbol for ordering information details, see page 12. cs sk org do di v cc gnd
cat93c76 (rev. a) doc. no. md-1090 rev. d 2 ? 2008 scillc. all rights reserved characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units temperature under bias ?55 to +125 oc storage temperature ?65 to 150 oc voltage on any pin with respect to ground (2) -2.0 to +v cc +2.0 v v cc with respect to ground -2.0 to +7.0 v lead soldering temperature (10 seconds) 300 oc output short circuit current (3) 100 ma reliability characteristics (3) symbol parameter reference test method min units n end (4) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (4) data retention mil-std-883, test method 1008 100 years v zap (4) esd susceptibility mil-std-883, test method 3015 2000 v i lth (4)(5) latch-up jedec standard 17 100 ma d.c. operating characteristics v cc = +1.8v to +5.5v unless otherwise specified. symbol parameter test conditions min typ max units i cc1 power supply current (write) f sk = 1mhz; v cc = 5.0v 1 3 ma i cc2 power supply current (read) f sk = 1mhz; v cc = 5.0v 300 500 a i sb1 power supply current (standby) (x8 mode) cs = 0v org = gnd 2 10 a i sb2 power supply current (standby) (x16mode) cs = 0v org = float or v cc 0 (6) 10 a i li input leakage current v in = 0v to v cc 0 (6) 10 a i lo output leakage current v out = 0v to v cc , cs = 0v 0 (6) 10 a i lorg org pin leakage current org = gnd or org = v cc 1 10 a v il1 input low voltage 4.5v v cc 5.5v -0.1 0.8 v v ih1 input high voltage 4.5v v cc 5.5v 2 v cc + 1 v v il2 input low voltage 1.8v v cc < 4.5v 0 v cc x 0.2 v v ih2 input high voltage 1.8v v cc < 4.5v v cc x 0.7 v cc + 1 v v ol1 output low voltage 4.5v v cc 5.5v; i ol = 2.1ma 0.4 v v oh1 output high voltage 4.5v v cc 5.5v; i oh = -400a 2.4 v v ol2 output low voltage 1.8v v cc < 4.5v; i ol = 100a 0.1 v v oh2 output high voltage 1.8v v cc < 4.5v; i oh = -100a v cc - 0.2 v notes: (1) stresses above those listed under ?absolut e maximum ratings? may cause permanent dam age to the device. these are stress rat ings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the minimum dc input voltage is ?0.5v . during transitions, inputs may undershoot to ?2.0v for periods of less than 20ns. m aximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20ns. (3) output shorted for no more than one second. (4) these parameters are tested initially and after a de sign or process change that affects the parameter. (5) latch-up protection is provided for stresse s up to 100 ma on i/o pins from ?1v to v cc +1v. (6) 0a is defined as less than 900na.
cat93c76 (rev. a) ? 2008 scillc. all rights reserved 3 doc. no. md-1090 rev. d characteristics subject to change without notice pin capacitance (1) symbol test conditions min typ max units c out output capacitance (do) v out = 0v 5 pf c in input capacitance (cs, sk, di, org) v in = 0v 5 pf instruction set (2) address data instruction start bit opcode x8 x16 x8 x16 comments read 1 10 a10-a0 a9-a0 read address an? a0 erase 1 11 a10-a0 a9-a0 clear address an? a0 write 1 01 a10-a0 a9-a0 d7-d0 d15-d0 write address an? a0 ewen 1 00 11xxxxxxxxx 11xxxxxxxx write enable ewds 1 00 00xxxxxxxxx 00xxxxxxxx write disable eral 1 00 10xxxxxxxxx 10xxxxxxxx clear all addresses wral 1 00 01xxxxxxxxx 01xxxxxxxx d7-d0 d15-d0 write all addresses a.c. characteristics limits v cc = 1.8v - 2.5v v cc = 2.5v - 5.5v symbol parameter test conditions min max min max units t css cs setup time 100 50 ns t csh cs hold time 0 0 ns t dis di setup time 100 50 ns t dih di hold time 100 50 ns t pd1 output delay to 1 250 150 ns t pd0 output delay to 0 c l = 100pf (3) 250 150 ns t hz (1) output delay to high-z 150 100 ns t ew program/erase pulse width 5 5 ms t csmin minimum cs low time 200 150 ns t skhi minimum sk high time 250 150 ns t sklow minimum sk low time 250 150 ns t sv output delay to status valid 250 100 ns sk max maximum clock frequency dc 1000 dc 3000 khz power-up timing (1)(4) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms notes: (1) these parameters are tested initially and after a de sign or process change that affects the parameter. (2) address bit a10 for the 1,024x8 org. and a9 for the 512x16 org. are ?don?t care? bits, but must be kept at either a ?1? or ?0? for read, write and erase commands. (3) the input levels and timing reference points are shown in the ?ac test conditions? table. (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated.
cat93c76 (rev. a) doc. no. md-1090 rev. d 4 ? 2008 scillc. all rights reserved characteristics subject to change without notice a.c. test conditions input rise and fall times 50ns input pulse voltages 0.4v to 2.4v 4.5v v cc 5.5v timing reference voltages 0.8v, 2.0v 4.5v v cc 5.5v input pulse voltages 0.2v cc to 0.7v cc 1.8v v cc 4.5v timing reference voltages 0.5v cc 1.8v v cc 4.5v device operation the cat93c76 is a 8192-bit nonvolatile memory intended for use with industry standard micropro- cessors. the cat93c76 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 13-bit instructions c ontrol the read, write and erase operations of the device. when organized as x8, seven 14-bit instructi ons control the read, write and erase operations of the device. the cat93c76 operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the risi ng edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ?1? into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organizations). the most significant bit of the address is ?don?t care? but it must be present. read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93c76 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). for the cat93c76, after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear a nd data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76 can be determined by selecting th e device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into.
cat93c76 (rev. a) ? 2008 scillc. all rights reserved 5 doc. no. md-1090 rev. d characteristics subject to change without notice figure 1. sychronous data timing figure 2. read instruction timing figure 3. write instruction timing sk di cs d o t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do high-z 11 0 a n a n-1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care sk cs di do t csmin standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew
cat93c76 (rev. a) doc. no. md-1090 rev. d 6 ? 2008 scillc. all rights reserved characteristics subject to change without notice erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76 can be determined by selecting th e device and polling the do pin. once cleared, the content of a cleared location returns to a logical ?1? state. erase/write enable and disable the cat93c76 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c76 writ e and clear instructions, and will prevent any accidental writing or clearing of the device. data can be re ad normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs w ill start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76 can be determined by selecting th e device and polling the do pin. once cleared, the contents of all memory bits return to a logical ?1? state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs w ill start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76 can be determined by selecting th e device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. note 1: after the last data bit has been sampled, chip select (cs) must be brought low before the next rising edge of the clock (sk) in order to start the self- timed high voltage cycle. this is important because if cs is brought low before or after this specific frame window, the addressed location will not be programmed or erased. power-on reset (por) the cat93c76 incorporates power-on reset (por) circuitry which protects the device against malfunctioning while v cc is lower than the recommended operating voltage. the device will power up in to a read-only state and will power-down into a re set state when vcc crosses the por level of ~1.3 v. figure 4. erase instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0
cat93c76 (rev. a) ? 2008 scillc. all rights reserved 7 doc. no. md-1090 rev. d characteristics subject to change without notice figure 5. ewen/ewds instruction timing figure 6. eral instruction timing figure 7. wral instruction timing sk cs di standby 10 0 * * enable=11 disable=00 sk cs di do standby t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t csmin d n d 0 0 0
cat93c76 (rev. a) doc. no. md-1090 rev. d 8 ? 2008 scillc. all rights reserved characteristics subject to change without notice package outline drawing s pdip 8-lead 300mils (l) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard ms-001. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification symbol min nom max a5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7.11 eb 7.87 10.92 l 2.92 3.30 3.80
cat93c76 (rev. a) ? 2008 scillc. all rights reserved 9 doc. no. md-1090 rev. d characteristics subject to change without notice soic 8-lead 150mils (v) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard ms-012. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 5.80 6.20 e1 3.80 4.00 e 1.27 bsc h 0.25 0.50 l 0.40 1.27 0o 8o symbol min nom max
cat93c76 (rev. a) doc. no. md-1090 rev. d 10 ? 2008 scillc. all rights reserved characteristics subject to change without notice tssop 8-lead 4.4mm (y) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard mo-153. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. a2 e1 e a1 e b d c a top view side view end view 1 l1 l symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 0.90 1.05 b0.19 0.30 c0.09 0.20 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e1 4.30 4.40 4.50 e 0.65 bsc l 1.00 ref l1 0.50 0.60 0.75 10 8
cat93c76 (rev. a) ? 2008 scillc. all rights reserved 11 doc. no. md-1090 rev. d characteristics subject to change without notice tdfn 8-pad 3 x 3mm (zd4) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard mo-229. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e2 a3 eb a a1 side view bottom view e d top view pin#1 index area pin#1 id front view a1 a l d2 symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.23 0.30 0.37 d 2.90 3.00 3.10 d2 2.20 ? 2.50 e 2.90 3.00 3.10 e2 1.40 ? 1.80 e0.65typ l 0.20 0.30 0.40
cat93c76 (rev. a) doc. no. md-1090 rev. d 12 ? 2008 scillc. all rights reserved characteristics subject to change without notice example of ordering information (1) notes: (1) all packages are rohs-compli ant (lead-free, halogen-free). (2) the standard lead finish is nipdau. (3) the device used in the above example is a 93c76vi-gt3 (soic, industrial temperature, nipdau, tape & reel, 3,000/reel) (4) product die revision letter is marked on top of the package as a suffix to the production date code (e.g., aywwa.) for addi tional information, please contact your on semiconductor sales office. (5) for tdfn 3 x 3mm package tape and reel = 2,000/reel, all others = 3,000/reel. (6) for additional package and temperatur e options, please contact your neares t on semiconductor sales office. prefix device # suffix cat 93c76 v i -g t3 company id product numbe r 93c76 temperature range i = industrial (-40oc to 85oc) e = extended (-40oc to 125oc) lead finish blank: matte-tin g: nipdau package l: pdip v: soic, jedec y: tssop zd4: tdfn (3 x 3mm) tape & reel t: tape & reel 2: 2,000 units/reel (5) 3: 3,000 units/reel for product top mark codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp
cat93c76 (rev. a) on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes with out further notice to any products herein. scillc make s no warranty, representa tion or guarantee regarding the suit ability of its products for any pa rticular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. sci llc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufact ure of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution ce nter for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center: phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? 2008 scillc. all rights reserved. 13 doc. no. md-1090 rev. d characteristics subject to change without notice revision history date rev. comments 11-aug-04 a initial issue 21-sep-07 b added package outline drawings updated the example of ordering information 30-apr-08 c update package outline drawings add top mark code link 29-oct-08 d change logo and fine print to on semiconductor

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